Field of the Invention
The present invention generally relates to integrated circuits, and, more specifically, to an approach for reducing power in floating-point operations of integrated circuits.
Description of the Related Art
A processor in a computer is typically configured to carry out floating-point operations for applications. For example, a conventional computer system may include a central processing unit (CPU) or a graphics processing unit (GPU) that is configured to carry out floating-point operations. A floating point is a way for a computer to represent a real number in a way that can support a wide range of values.
The term floating-point refers to the fact that the decimal point (or binary point) can “float”. For example, a processor can place the decimal point anywhere relative to the significant digits of the number. This position is indicated separately in the internal representation of the floating-point number. Accordingly, floating-point representation may be thought of as a computer realization of scientific notation. Over the years, computer engineers have used a variety of floating-point representations in computers. Since the 1990s, the most commonly encountered representation is that defined by the Institute of Electrical and Electronics Engineers (IEEE) 754 Standard.
Processors that carry out floating-point operations typically must be compliant with standards of the IEEE 754 Standard. In high-performance computing, full IEEE-precision and rounding compliance is necessary. Unfortunately, such support comes with a cost in both area and power consumption on an integrated circuit. The cost is an extra burden particularly when the computations being performed do not require the precision and rounding compliance set forth by a standard.
As the foregoing illustrates, what is needed in the art is a more efficient approach to performing floating point operations in computer systems.